@jcm@wafrn.jcm.re asked

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1') ); end my_code; architecture rtl of my_code is -- Internal signals for color channels signal r_sig : std_logic_vector(7 downto 0); signal g_sig : std_logic_vector(7 downto 0); signal b_sig : std_logic_vector(7 downto 0); -- Animation state signals signal frame_counter : unsigned(31 downto 0) := (others => '0'); signal anim_speed : integer range 0 to 3 := 0; -- Bouncing text state constant msg_text : string := " ❤ VHDL ❤ "; signal text_col : integer range -10 to CONSOLE_COLUMNS + 10 := 5; -- widened range for safety signal text_row : integer range -10 to CONSOLE_ROWS + 10 := 5; signal dir_col : integer range -1 to 1 := 1; signal dir_row : integer range -1 to 1 := 1; begin -- Assemble background color from internal signals background_color <= r_sig & g_sig & b_sig; -- Foreground is always white foreground_color <= (others => '1'); ---------------------------------------------------------------------------- -- 1. Background Generation -- Calculates Manhattan distance using IF/ELSE to avoid 'abs' synthesis error. ---------------------------------------------------------------------------- process(px, py, frame_counter) variable dx, dy : integer; variable dist : integer; variable phase : unsigned(7 downto 0); begin -- Manual Absolute Value for X if px > (WIDTH / 2) then dx := px - (WIDTH / 2); else dx := (WIDTH / 2) - px; end if; -- Manual Absolute Value for Y if py > (HEIGHT / 2) then dy := py - (HEIGHT / 2); else dy := (HEIGHT / 2) - py; end if; dist := dx + dy; -- Create moving phase phase := to_unsigned((dist / 2) - to_integer(frame_counter(7 downto 0)), 8); -- Assign colors r_sig <= std_logic_vector(phase + 128); g_sig <= std_logic_vector(phase); b_sig <= std_logic_vector(phase - 128); end process; ---------------------------------------------------------------------------- -- 2. Foreground Text Generation ---------------------------------------------------------------------------- process(col, row, text_col, text_row) variable char_index : integer; begin char <= 0; if (row = text_row) and (col >= text_col) and (col < text_col + msg_text'length) then char_index := col - text_col + 1; char <= character'pos(msg_text(char_index)); end if; end process; ---------------------------------------------------------------------------- -- 3. Animation Logic ---------------------------------------------------------------------------- process(clk) variable old_vsync : std_logic := '0'; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; -- Update position every few frames if anim_speed = 2 then anim_speed <= 0; -- Check Horizontal Bounds if (dir_col = 1 and (text_col + msg_text'length >= CONSOLE_COLUMNS - 1)) then dir_col <= -1; elsif (dir_col = -1 and text_col <= 1) then dir_col <= 1; else text_col <= text_col + dir_col; end if; -- Check Vertical Bounds if (dir_row = 1 and (text_row >= CONSOLE_ROWS - 2)) then dir_row <= -1; elsif (dir_row = -1 and text_row <= 1) then dir_row <= 1; else text_row <= text_row + dir_row; end if; else anim_speed <= anim_speed + 1; end if; end if; old_vsync := vsync; end if; end process; end architecture;

Sucess!Utilization

Timing

Codelibrary ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
generic(
WIDTH : integer := 640;
HEIGHT : integer := 480;
CONSOLE_COLUMNS : integer := WIDTH / 8;
CONSOLE_ROWS : integer := HEIGHT / 8
);
port(
clk : in std_logic;
rst : in std_logic;
px : in integer range 0 to WIDTH - 1;
py : in integer range 0 to HEIGHT - 1;
hsync : in std_logic;
vsync : in std_logic;
col : in integer range 0 to CONSOLE_COLUMNS - 1;
row : in integer range 0 to CONSOLE_ROWS - 1;
char : out integer range 0 to 127 := 0;
foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
background_color : out std_logic_vector(23 downto 0) := (others => '1')
);
end my_code;

architecture rtl of my_code is
-- Internal signals for color channels
signal r_sig : std_logic_vector(7 downto 0);
signal g_sig : std_logic_vector(7 downto 0);
signal b_sig : std_logic_vector(7 downto 0);

-- Animation state signals
signal frame_counter : unsigned(31 downto 0) := (others => '0');
signal anim_speed    : integer range 0 to 3 := 0;

-- Bouncing text state
constant msg_text    : string := " <3 VHDL <3 ";
signal text_col      : integer range -10 to CONSOLE_COLUMNS + 10 := 5; -- widened range for safety
signal text_row      : integer range -10 to CONSOLE_ROWS + 10 := 5;
signal dir_col       : integer range -1 to 1 := 1;
signal dir_row       : integer range -1 to 1 := 1;

-- Assemble background color from internal signals
background_color <= r_sig & g_sig & b_sig;

-- Foreground is always white
foreground_color <= (others => '1');

----------------------------------------------------------------------------
-- 1. Background Generation
-- Calculates Manhattan distance using IF/ELSE to avoid 'abs' synthesis error.
----------------------------------------------------------------------------
process(px, py, frame_counter)
    variable dx, dy : integer;
    variable dist   : integer;
    variable phase  : unsigned(7 downto 0);
begin
    -- Manual Absolute Value for X
    if px > (WIDTH / 2) then
        dx := px - (WIDTH / 2);
    else
        dx := (WIDTH / 2) - px;
    end if;

    -- Manual Absolute Value for Y
    if py > (HEIGHT / 2) then
        dy := py - (HEIGHT / 2);
    else
        dy := (HEIGHT / 2) - py;
    end if;

    dist := dx + dy;

    -- Create moving phase
    phase := to_unsigned((dist / 2) - to_integer(frame_counter(7 downto 0)), 8);

    -- Assign colors
    r_sig <= std_logic_vector(phase + 128);
    g_sig <= std_logic_vector(phase);
    b_sig <= std_logic_vector(phase - 128);
end process;

----------------------------------------------------------------------------
-- 2. Foreground Text Generation
----------------------------------------------------------------------------
process(col, row, text_col, text_row)
    variable char_index : integer;
begin
    char <= 0; 

    if (row = text_row) and 
       (col >= text_col) and 
       (col < text_col + msg_text'length) then

        char_index := col - text_col + 1;
        char <= character'pos(msg_text(char_index));
    end if;
end process;

----------------------------------------------------------------------------
-- 3. Animation Logic
----------------------------------------------------------------------------
process(clk)
    variable old_vsync : std_logic := '0';
begin
    if rising_edge(clk) then
        if vsync = '0' and old_vsync = '1' then
            frame_counter <= frame_counter + 1;

            -- Update position every few frames
            if anim_speed = 2 then
                anim_speed <= 0;

                -- Check Horizontal Bounds
                if (dir_col = 1 and (text_col + msg_text'length >= CONSOLE_COLUMNS - 1)) then
                    dir_col <= -1;
                elsif (dir_col = -1 and text_col <= 1) then
                    dir_col <= 1;
                else
                    text_col <= text_col + dir_col;
                end if;

                -- Check Vertical Bounds
                if (dir_row = 1 and (text_row >= CONSOLE_ROWS - 2)) then
                    dir_row <= -1;
                elsif (dir_row = -1 and text_row <= 1) then
                    dir_row <= 1;
                else
                    text_row <= text_row + dir_row;
                end if;

            else
                anim_speed <= anim_speed + 1;
            end if;
        end if;

        old_vsync := vsync;
    end if;
end process;

#FPGA #Icepi-Zero #HDL #VHDL