CPU and Memory use clock speed regulated by voltage to pass data back and forth with no gates between

could you please explain what you mean by no gates?

(ok i see, you're using the term CPU colloquially to refer to the processor. i know you obviously know the difference & that's what you meant - i just mention the distinction for others who may not be aware.)

ultimately op may not require exact monitoring, since they compared it to standard system monitors etc, which are ofc approximate as well. so the tools as listed by Eager Eagle in this comment may be sufficient for the general use described by op?

eg. these, screenshots looks pretty close to what i imagined op meant

now onto your very cool idea of substantially improving the temporal resolution of measuring memory bandwidth...you've got me very interested with your idea 😀

my inital sense is counting completed L3/4 cache misses sourced from DRAM and similar events might be alot easier - though as you point out that will inevitably accumulate event counts within a given time interval rather than an individual event.

i understand the role of parity bits in ECC memory, but i didn't quite understand how & which ECC fields you would access, and how/where you would store those results with improved temporal resolution compared to event counts?

would love to hear what your setup would look like? 😀 which ECC-specific masks would you monitor? where/how would you store/process such high resolution results without impacting the measurement itself? details pls 😁

Eager Eagle

2025-05-23 22:50:34

It seems pcm-memory can do it on Intel CPUs and uProf for AMD.

Other than these I've mostly seen benchmarking and profiling tools (like perf) but I guess these are not what you're looking for.

GitHub - intel/pcm: Intel® Performance Counter Monitor (Intel® PCM)

Intel® Performance Counter Monitor (Intel® PCM). Contribute to intel/pcm development by creating an account on GitHub.

^GitHub