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snac - Link to source

High speed of development of Huawei's phone CPUs, 3 generations of chips in 2 years

Sidenote: its insane how chipmakers refer to CPUs as 7 nanometer, 2 nanometer, etc, since there is absolutely no component or wire inside the CPU that is actually this small, it purely a marketing term lol

wccftech.com/kirin-9030-for-th…


Huawei’s Kirin 9030 For The Upcoming Mate 80 Flagship Smartphone Series Is Rumored To Provide A 20 Perce…

A new rumor claims that Huawei is developing the Kirin 9030 for the Mate 80 lineup and it is allegedly 20 percent faster than the previous generation
Wccftech
in reply to 💙🩷💜Ⓑⓡⓔⓣⓣ🐡🍉🐧

friendica (DFRN) - Link to source

Nanook

@💙🩷💜Ⓑⓡⓔⓣⓣ🐡🍉🐧 Actually it does. It refers to the minimum grid size that all the structures are drawn on before they are fabricated using photo lithography. Usually transistor gate length is two times this minimum size. So it directly refers to the number of transistors that you can fit into a given area. It should be noted that this is true for most logic transistors but usually silicon compilers will have several different transistor designs for low current high switch speed, and high current but not as fast as switching, the latter often being used for things like bus drivers, and these will be physically larger.
in reply to Nanook

snac - Link to source

💙🩷💜Ⓑⓡⓔⓣⓣ🐡🍉🐧

the critical word there being "area" which is 2D measure while a CPU is a 3D structure.

ie to use a human-size example, if my waist circumference is 90cm and someone stands on my shoulders at a 1cm offset that does not make my waist circumference 90cm+1cm/2 = 45.5cm even though I now fit just under twice as many ppl in the same "area"

CPU makers use exactly the same accounting trick to claim (e.g.) 2 nanometer "nodes"

in reply to 💙🩷💜Ⓑⓡⓔⓣⓣ🐡🍉🐧

friendica (DFRN) - Link to source

Nanook

@💙🩷💜Ⓑⓡⓔⓣⓣ🐡🍉🐧 We do not yet have the technology to effectively stack transistors, so although they are 3D, they are not more than one transistor high, though other things like interconnects, power, and ground may be above them. What is important is the number of transistors scale up as the node sizes reduce.
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